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VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
64x64 Crosspoint Switch
VSC6464
Features
* Synchronous or Asynchronous Operation * 500Mb/s Asynchronous Operation * 250Mb/s Synchronous Operation * <750ps Output to Output Skew (Synchronous) * <1.5ns Skew Input to Output (Asynchronous) * Single Ended ECL I/O * Separate Input and Output Register Clocks * Single Supply: -2V + 5% @ 8 Watts (Max.) * Commercial (0o to +70oC) Temperature Range * Package: 208PQFP
General Description
The VSC6464 is a 64x64 asynchronous (flow-through) or synchronous (clocked) high-speed crosspoint switch. Any input can be multiplexed to any, some, or all outputs. The switch is fully non-blocking. All I/Os are single-ended ECL. The part is packaged in a 208-pin plastic quad flat pack and consumes less than 8 Watts from a single -2V power supply. In the asynchronous mode, high speed digital data up to 500Mb/s can be switched with less than 25% pulse width distortion. Skew is less than 1.5 ns between any two paths through the switch. In broadcast operation (one input routed to two or more outputs), any two outputs will exhibit less than 750ps of skew. In the synchronous mode, high-speed digital data up to 250 Mb/s can be switched with less than 750ps output-to-output skew. The input and output registers have separate clock inputs.
VSC6464 Functional Block Diagram
MODE DIN<63:0> 2:1 MUX REG 64 x 64:1 MUX REG 2:1 MUX DOUT<63:0>
CKI CKO SERS SERD SERC
SERIAL TO PARALLEL
DEC
64 6-BIT REGISTERS
G52219-0, Rev. 2.0 8/4/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
64x64 Crosspoint Switch
Advance Product Information
VSC6464
Functional Description
This Crosspoint Switch connects any of the 64 inputs to any combination of 64 output channels, according to a user defined bit pattern stored in each channel's control register. Signals from the 64 inputs (DIN_0 through DIN_63) are connected to the 64 output channels (DOUT_0 through DOUT_63) through sixty-four 64:1 multiplexers. The traffic pattern is controllable by data stored in sixty-four 6-bit control registers with each register corresponding to an output channel. The six bits are a binary numerical representation of the input channel selected (i.e.: 000000 corresponds to DIN_0, 000001 corresponds to DIN_1, etc.). An additional six bit register is used to address the output channel being programmed. These six bits are a binary numerical representation of the output channel (ie.: 000000 corresponds to DOUT_0, 000001 corresponds to DOUT_1, etc.). All twelve configuration bits are loaded through a three-pin serial port. The crosspoint is configured through a serial data port consisting of three pins: SERS, SERC, and SERD. SERS is used to select the crosspoint for configuration. SERC is a serial clock signal whose rising edge samples the serial data on SERD when SERS is active (HI). The serial data stream applied to SERD consists of the six bits of address, followed by the six bits of data. Address information is used to identify one of the 64 output channels, a valid value is between 0 and 63. Data information selects a specific input to be directed to the addressed output, valid values are between 0 and 63. Both address and data information are received MSB first. A serial load cycle consists of activating serial select (SERS), pulsing serial clock 12 times (with valid data surrounding each rising edge), then deactivating serial select (SERS). Deactivating serial select before the twelfth rising edge of SERC will abort the load cycle. Serial select (SERS) must be deactivated for 10ns following a power up. Any additional clocking of SERC during a load cycle, beyond that described above, is ignored. The MODE pin determines the operating mode of the Crosspoint: synchronous or asynchronous, as shown in Table 1. A test output (TESTO) is provided for internal visibility, this signal will go high when a thirteenth rising edge is applied during a load cycle; TESTO goes low when either SERS is lowered, or a fourteenth SERC edge is received during a load cycle. This output can be left unconnected if desired, to reduce noise and power dissipation.
Table 1: Crosspoint Mode (MODE) Function
Asynchronous 64x64 Synchronous 64x64
MODE
0 1
Page 2
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52219-0, Rev. 2.0 8/4/98
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
64x64 Crosspoint Switch
VSC6464
AC Characteristics (Over recommended operating conditions)
Figure 1 Output Loading
Output 4pF 50
VTT
Figure 2 VSC6464 Configuration Timing Diagram
SERC TSS SERS TDS TDH SERD A5 A4 A3 A2 A1 A0 D5 D4 D3 D2 D1 D0 TSH
Note: A5 is MSB of A<5:0>, D5 is MSB of D<5:0>.
Table 2: VSC6464 Asynchronous Timing Table Parameters
TSS TSH TDS TDH
Description
SERS setup time with respect to SERC SERS hold time with respect to SERC SERD setup time with respect to SERC SERD setup time with respect to SERC
Min
10 10 10 10
Typ
-
Max
-
Units
ns ns ns ns
G52219-0, Rev. 2.0 8/4/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
64x64 Crosspoint Switch
Advance Product Information
VSC6464
Figure 3 VSC6464 Asynchronous Timing Diagram T PW DIN<63:0> T AMX DOUT<63:0> TAMN TASKW Table 3: VSC6464 Asynchronous Timing Table Parameters
TPW TAMX TAMN TASKW TASKW -
Description
Minimum DIN<63:0> pulse width, 50% input DIN<63:0> to DOUT<63:0> propagation delay DIN<63:0> to DOUT<63:0> propagation delay DOUT<63:0> asynchronous mode data skew (any input to any output, add 0.1 for SSO) DOUT<63:0> asynchronous mode data skew (broadcast, add 0.1 for SSO) Duty Cycle Distortion, @500Mb/s(1)
Min
1.25 2.2 -
Typ
-
Max
6.5 1.4 0.75 25
Units
ns ns ns ns ns %
Note: 1.) Duty cycle distortion = (duty cycle in - duty cyle out)/duty cycle in * 100%, measured with a 2ns pulse width.
Figure 4 VSC6464 Synchronous Data Input Timing Diagram
CKI
TINSU T INH DIN<63:0>
Table 4: VSC6464 Synchronous Data Input Timing Table Parameters
FMAX TINSU TINH
Description
Maximum CKI frequency, 50% input DIN<63:0> data setup time with respect to CKI DIN<63:0> data hold time with respect to CKI
Min
0.5 0.4
Typ
-
Max
250 -
Units
MHz ns ns
Page 4
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52219-0, Rev. 2.0 8/4/98
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
64x64 Crosspoint Switch
VSC6464
Figure 5 VSC6464 Synchronous Data Output Timing Diagram
CKO
T SMX DOUT<63:0> TSMN TSSKW Table 5: VSC6464 Synchronous Data Output Timing Table Parameters
FMAX TSMX TSMN TSSKW
Description
Maximum CKO frequency, 50% input Maximum propagation delay CKO toDOUT<63:0> Minimum propagation delay CKO to DOUT<63:0> DOUT<63:0> synchronous mode data skew (add 0.1 for SSO)
Min
1.4 -
Typ
-
Max
250 3.7 0.75
Units
MHz ns ns ns
Figure 6 VSC6464 Synchronous Mode Clock Relationship
T CKI TCC
CKO
Table 6: VSC6464 Synchronous Data Output Timing Table Parameters
TCC
Description
CKO relative to CKI, 50% input
Min
0.1
Typ
-
Max
0.8
Units
ns
Note: A nominal delay of 0.25 ns between input and output clocks can be achieved by a trace on the pc board run directly from the input clock pin to the output clock pin. In this case, the clock signal should be connected to the input pin with the delay supplied by the pc board trace.
G52219-0, Rev. 2.0 8/4/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 5
VITESSE
SEMICONDUCTOR CORPORATION
64x64 Crosspoint Switch
Advance Product Information
VSC6464
DC Characteristics
Table 7: ECL Inputs and Outputs Parameter Description
Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input HIGH current Input LOW current
Min
-1020 -2000 -1100 -2000 -50
Typ
-
Max
-700 -1620 -700 -1540 200 -
Units
mV mV mV mV uA uA
Conditions
VIN=VIH (max) VIN=VIL (min)
VOH VOL VIH VIL IIH IIL
Power Dissipation
Table 8: VSC6464 Power Supply Currents Parameter
ITT PD Power supply current from VTT Power dissipation (Note: Specified with outputs open circuit.)
Description
(Max)
3.8 8
Units
A W
Absolute Maximum Ratings(1)
Power Supply Voltage (VTT) Potential to GND ............................................................................. -2.5 V to +0.5 V ECL Input Voltage Applied ................................................................................................... +0.5 V to VTT -0.5 V Output Current (IOUT) ................................................................................................................................... 50 mA Case Temperature Under Bias (TC) ................................................................................................-55o to + 125oC Storage Temperature (TSTG)............................................................................................................-65o to + 150oC
Note: Caution: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect device reliability.
Recommended Operating Conditions
Power Supply Voltage (VTT) ................................................................................................................ -2.0 V+0.1V Commercial Operating Temperature Range* (T) .................................................................................. 0o to 70oC
* Lower limit of specification is ambient temperature and upper limit is case temperature.
ESD Ratings
Proper ESD procedures should be used when handling this product. The VSC6464 is rated to the following ESD voltages based on the human body model: 1. All pins are rated at or above 1500V.
Notes: 1) Load=50 to -2.0V.
Page 6
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52219-0, Rev. 2.0 8/4/98
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
64x64 Crosspoint Switch
VSC6464
Pin Descriptions
Table 9: Pin Identification Signal Pin
2-5, 15, 18, 24, 28, 29, 35, 38, 4851, 61-63, 69, 72, 75, 79, 82, 85, 88, 94-96, 106-109, 119, 122, 128, 132, 133, 139, 142, 152-155, 165-167, 173, 176, 179, 183, 186, 189, 192, 198-200 8, 21, 27, 32, 45, 57, 78, 100, 112, 125, 131, 136, 149, 161, 182, 204 156-160, 162-164, 201-203, 205207, 1, 12-14, 16-17, 19-20, 22-23, 25, 30-31, 33-34, 36-37, 39-40, 5256, 58-60, 97-99, 101-105, 118, 120-121, 123-124, 126-127, 129, 134-135, 137-138, 140-141, 143 10-9, 7-6, 197-193, 191-190, 188187, 185-184, 181-180, 178-177, 175-174, 172-168, 151-150, 148145, 116-113, 111, 93-89, 87-86, 84-83, 81-80, 77-76, 74-73, 71-70, 68-64, 47-46, 44-42 117 11 41 26 130 144 110 208
I/O
Description
VCC
0V Ground Connection.
VTT
-2V Supply Connection.
DIN_0-DIN_63
I
The 64 ECL Signal Inputs.
DOUT_0DOUT_63
O
The 64 ECL Signal Outputs.
SERS SERC SERD CKI CKO MODE TESTO VSCTE
I I I I I I O I
ECL Serial Select Signal ECL Serial Clock Signal. ECL Serial Data Signal. ECL Synchronous Mode Input Register Clock Signal. ECL Synchronous Mode Output Register Clock Signal. ECL Synchronous Mode Enable Signal. do not use. test input, connect to -2V for normal operation
G52219-0, Rev. 2.0 8/4/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 7
VITESSE
SEMICONDUCTOR CORPORATION
64x64 Crosspoint Switch
Advance Product Information
VSC6464
Package Information
The VSC6464 is packaged in a 208 PQFP with an integral heat sink as shown in the figure below.
208 PQFP Package Drawing
PIN 208
HEATSINK INTRUSION NOTE 1 157 156
PIN 1
Key
A A1 A2 D
E1 E
mm
4.07 0.25 3.49 30.60 28.00 30.60 28.00 0.60 0.50 0.22 0 - 10 .15 .25
Tolerances
MAX MIN .10 .4 .10 .4 .10 +.15/-.10 BASIC .05 TYP MAX
D1 E E1 L e
52 53 104
105
b R1 R
D1 D
TOP VIEW
10
A2
e
10
R
R1
0 MIN
A
0.25
A1
0.17 MAX
L b
NOTES: (1) Exposed Heatspreader will be either 20.32 .50 round or 12.0 .50 square (2) Drawing not to scale. Package #: 101-228-6, Issue #:1
Page 8
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52219-0, Rev. 2.0 8/4/98
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
64x64 Crosspoint Switch
VSC6464
Thermal Information
Figure 7 CA vs Air Velocity for the 208 PQFP (28mmx28mmx3.2mm)
25
Case to Air Thermal Resistance (oC/W)
20
Air Vel. LFPM
0 100 200
Theta(ca) oC/W
21.8 15.8 13.8 10.7 9.5
15
10
400 600
5
200 400 600 Air Velocity (LFPM) CA measurement method: Semi-standard G38-87, in a wind tunnel Semi-standard G42-88/JEDEC JC 15.1 #1 FR4 PCB 3"x4.5"x0.62" 0
0
Notice
This document contains information about a product during its fabrication or early sampling phase of development. The information contained in this document is based on design targets, simulation results or early prototype test results. Characteristic data and other specifications are subject to change without notice. Therefore the reader is cautioned to confirm that this datasheet is current prior to design or order placement.
Warning
Vitesse Semiconductor Corporation's product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited.
G52219-0, Rev. 2.0 8/4/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 9
VITESSE
SEMICONDUCTOR CORPORATION
64x64 Crosspoint Switch
Advance Product Information
VSC6464
Application Notes
Figure 8 Multiple-Crosspoint Synchronous System Configuration
SYSTEM_CK
CKO CKI
REG DATA_IN
DIN SERS
XPNT0
DOUT SERD MODE SERC
REG DATA_OUT
XPNT_0_SEL SERIAL_CK MODE = `1' SERIAL_DATA XPNT_1_SEL
SERC MODE SERD SERS
REG DATA_IN
XPNT1
DIN DOUT CKO
REG DATA_OUT
SYSTEM_CK
High-speed designs using single-ended ECL signals need careful design to avoid noise and crosstalk problems. The following suggestions can aid obtaining a reliable system: 1. Wide noise margins on input signals. 2. Avoid SSOs. Simultaneous switching outputs will degrade timing margins by increasing AC delay values, and reducing noisethresholds. 3. Provide good signal terminations and well-matched board traces in addition to well-controlled power supplies.
Page 10
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
CKI
G52219-0, Rev. 2.0 8/4/98

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